Riviera-PRO is a comprehensive design and verification environment that provides a robust platform for designing, simulating, and verifying complex digital systems. The tool supports a wide range of design languages, including VHDL, Verilog, SystemVerilog, and mixed-language designs. With its advanced features and capabilities, Riviera-PRO enables designers to efficiently develop and verify their designs, reducing the risk of errors and functional issues.

: Riviera-PRO is designed to scale with the needs of the project, supporting the verification of designs of varying complexities.

Full support for SVA and PSL to increase design observability and reduce the time spent identifying errors.